Junior (Student) Design Verification

As a member of our dynamic group, you will have the opportunity of learning and work as Verification Engineer in high-tech FPGA and ASIC designs. The responsibilities include verification environment development including stimulus and checkers, simulations, debugging, and documentation.

Key Qualifications

• Basic knowledge of some HDL Language.
• Advanced knowledge of OOP (C/C++).
• Knowledge of some scripting languages (Python, Perl, Bash..).
• English Intermediate.
• Humanly, you have to enjoy working in a team.

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Education & Experience

• Engineering student or recent graduate.

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If you are interested send your CV to the email: rrhh@emtech.com.ar with the name of the position in the subject.

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