Junior (Student) RTL Design

As a member of our dynamic group, you will have the opportunity of learning and work as RTL Engineer in high-tech FPGA and ASIC designs.

Key Qualifications

  • Good understanding of digital design concepts
  • Basic knowledge of some HDL language (VHDL or Verilog/SystemVerilog)
  • Basic knowledge of scripting languages such Python, Tcl, or Bash
  • Good use of English for communicating ideas and documenting
  • Ability to work proactively and collaboratively in a team environment


  • Design and implement RTL modules for various technologies
  • Verify and validate the RTL design using simulation tools
  • Debug designs using laboratory instruments such oscilloscopes and logic analyzers
  • Automate design tools using scripts
  • Use existing documentation and generate documentation for new designs

Education & Experience

  • The candidate should have a degree or be an advanced student in electronic engineering, computer engineering, telecommunications engineering or another related field.
  • Experience with digital design during university or as a hobbyist is a plus.

If you are interested send your CV to the email: rrhh@emtech.com.ar with the name of the position in the subject.