Semi Senior Design Verification Engineer

As a member of our dynamic group, you will have the opportunity to work as Design Verification Engineer in high-tech FPGA and ASIC designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Key Qualifications

  • Advanced knowledge of SystemVerilog and UVM
  • Experience with SVA and Functional Coverage.
  • Background in design techniques Verilog or VHDL.
  • Verification EDA tools, Verification methodologies, Verification IPs.
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations.
  • Proficiency in scripting Python, TCL Perl, Bash…
  • Good level in English, both writing and oral skills
  • Humanly, you have to enjoy working in a team.

Education & Experience

  • MSEE degree + 2 years of industrial experience
  • BSEE degree + 3 years of industrial experience

If you are interested send your CV to the email: with the name of the position in the subject.