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14 posts found

Integrating Wireshark with UVM: A High-Level Overview
Integrating Wireshark with UVM: A High-Level Overview

Integrating Wireshark with UVM: A High-Level Overview One of the key challenges...


FPGA Verification

July 1, 2026

DPI, Python, and Wireshark Integration
DPI, Python, and Wireshark Integration

In previous blogs, we have explained the fundamentals of DPI and how...


FPGA Verification

July 1, 2026

UVM Factory
UVM Factory

The UVM Factory is a software design pattern employed in UVM. It...


FPGA Verification

July 1, 2026

UVM Config Database
UVM Config Database

The `UVM_config_db` is a global database that stores key-value pairs, similar to...


FPGA Verification

July 1, 2026

UVM Phases
UVM Phases

UVM phases are virtual methods defined within the `uvm_component` class. This class...


FPGA Verification

July 1, 2026

Generating a random variable with uniformly distributed maximum over a window with configurable size
Generating a random variable with uniformly distributed maximum over a window with configurable size

In verification, when testing a device with random inputs, it is important...


FPGA Verification

July 1, 2026

From Tedious to Triumphant: Automating UVM Register Models with PeakRDL
From Tedious to Triumphant: Automating UVM Register Models with PeakRDL

Modern digital designs, especially complex System-on-Chip (SoCs), can contain hundreds or even...


FPGA Verification

December 4, 2025

Virtual sequences and virtual sequencers: Part 2
Virtual sequences and virtual sequencers: Part 2

In modern verification environments, UVM sequences serve as the backbone of stimulus...


FPGA Verification

March 28, 2025

UVM: Monitoring/Binding DUT Internal Signals
UVM: Monitoring/Binding DUT Internal Signals

There are three approaches related to functional verification: black-box, white-box, and gray-box....


FPGA Verification

March 28, 2025

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