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10 posts found

From Tedious to Triumphant: Automating UVM Register Models with PeakRDL
From Tedious to Triumphant: Automating UVM Register Models with PeakRDL

Modern digital designs, especially complex System-on-Chip (SoCs), can contain hundreds or even...

RTL Verification

December 4, 2025

Virtual sequences and virtual sequencers: Part 2
Virtual sequences and virtual sequencers: Part 2

In modern verification environments, UVM sequences serve as the backbone of stimulus...

RTL Verification

March 28, 2025

UVM: Monitoring/Binding DUT Internal Signals
UVM: Monitoring/Binding DUT Internal Signals

There are three approaches related to functional verification: black-box, white-box, and gray-box....

RTL Verification

March 28, 2025

SOLID Principles in SystemVerilog for Verification
SOLID Principles in SystemVerilog for Verification

In this article, we will explore how to apply the SOLID principles...

RTL Verification

March 28, 2025

Randomization with Systemverilog – Second Part
Randomization with Systemverilog – Second Part

Discover how to effectively use the unique constraint and explore various methods...

RTL Verification

March 28, 2025

Randomization with Systemverilog
Randomization with Systemverilog

Developing a test where simulation parameters are randomized enables achieving better coverage...

RTL Verification

March 28, 2025

Defining Strategy with Verification and RTL Teams
Defining Strategy with Verification and RTL Teams

I’ve been working closely with our Verification and RTL teams to set...

RTL Verification

March 28, 2025

DPI basics – Part 1
DPI basics – Part 1

DPI (Direct Programming Interface) in SystemVerilog enables seamless integration with C, Python,...

RTL Verification

March 28, 2025

DPI basics – Part 1
DPI basics – Part 1

DPI (Direct Programming Interface) in SystemVerilog enables seamless integration with C, Python,...

RTL Verification

March 28, 2025