Our ASIC verification services encompass thorough testing and validation, guaranteeing the reliability and performance of your design.

An ineffective verification strategy can consume valuable time and resources. Therefore, it is crucial to depend on expertise and experience. With over 15 years of experience and a profound understanding of the verification discipline, we recognize that the cornerstone of successful ASIC design and development is the careful selection of effective verification criteria.

Our verification engineers have mastered several ASIC verification strategies and guidelines that allow customers rapid and reliable closure of the verification effort for the most complex ASICs.


algorithms and modeling


  • VHDL
  • System Verilog
  • Verilog
  • HLS
  • Scripting (TCL, Python,...)
  • C/C++
  • High Level Languages
  • Matlab
  • UVM
  • OVM
Algorithms & Modelling
Physical layout
Verification icon
Implementation and testing icon
Physical Layout
Implementation & Testing

development cycle

Asic Development Cycle


UVM-based functional verification of two ASIC designs

Two ASIC designs of more than 100 million gates each, on a 7 nm TSMC process.
-Migration of legacy UVM/OVM environments to new environments
-Generation and implementation of the pre-silicon test plan (blocks and full-chip), including execution and management (Jira and GitHub)
-Cadence’s VIPs integration for an AlphaWave PCIe controller (5Gen), I2C and SPI-IP interfaces, into the verification flow for both ASICs.
-System integration and verification of a Tensilica microcontroller IP including integration of SRAM.
-Platform-level validation of the controller (using new firmware).

Diffraction representing SAR emulation
SAR RADAR Target Emulation

System implementation of algorithms and signal processing techniques to generate SAR RADAR data, simulating the transmitted and received signals as obtained from a real SAR antenna.

FPGA implementation includes: beam-forming, polarization, bandwidth, and beam steering.

Our expertise

  • Self Testing Systems
  • Limited Random Testing
  • Functional Coverage Analysis
  • SV Assertion-Based Verification
  • Gate-level simulations and Regression Management
  • Verification and test plan developments
  • Power-aware verification
  • Full Verification (UVM, testbench design, debug support)
  • Extensive experience with all advanced EDA tools for verification from all major EDA tool suppliers
  • System Modelling
  • EDA tool flow consulting
  • UVM and OBM Languages
  • Analysis and coverage closure
  • IP and SOC-level Verification using C/C++, SV-UVM methodologies (UVM 1.1, 1.2) 

CORE DESIGN methodology

AmD Xilinx Logo white and black
Microchip Logo
Siemens logo Black and white
Logo Universal Verification Methodology
Intel FPGA
Logo Intel Quartus and synopsys

FIELDS of interest

Satellite communications

Satellite Communication

Satellite platform  image

Satellite Platform

High performance computer image

High Performance Computing

Industrial systems icon

Industrial Instrumentation & Control


Cloud system icon

Cloud Systems

Video Streaming logo

Video Streaming

Radar icon


Sensor acquisition icon

Sensor Adquisition & Procesing

Communications icon


IOT icon


mobile icon


Test system icon

Test Systems