ASIC Design

We deliver top-notch ASIC design services that encompass the entire development process, from inception to execution.

With 15+ years of experience and a deep understanding of the development cycle, we excel at transforming concepts into robust implementations.

A 25+ professional digital ASIC design team with combined experience of more than 50 tape-outs in nodes from 180 nm all the way down to 3 nm, and a solid management team with more than 15 years in the microelectronics and SoC solutions industry.

Our methodology adapts to clients' demands, from thorough procedures to rapid developments.

We have a proven track record across diverse industries, including new space, aerospace & defense, nuclear, industrial, and healthcare


architectural specification
RTL,  logic and physical synthesis
algorithms and modeling
SoC and Sub-system Integration


  • Verilog
  • System Verilog
  • VHDL
  • HLS
  • Scripting (TCL, Python,...)
  • C/C++
  • High Level Languages
  • Matlab


  • CMOS HV 350nm, 180nm, XFAB
  • CMOS 180nm, 130nm, Global Foundries
  • CMOS 65nm down to 3nm, Intel, TSMC


  • HSIO Protocols (PCIe, OmniPath), AMBA protocols (AXI/AHB/APB)
  • High speed SERDES interfacing
  • Memory interfaces (DDRx/LPDDRx)
  • Low-speed peripheral interfaces (I2C, SPI, UART, MDIO, I2S)
Physical layout
IP Block Design and Development
Verification icon
Low-power design & checks & Automated property checks
Implementation and testing icon
Lint, CDC
DFT insertion, ATPG
Implementation and testing icon
Clock and reset design, Clock gating, UPF
post-silicon testing writing

development cycle


Silicon-tested ultra-low-power RISC-V based microcontroller on a 0.18um and 65nm

-Silicon-tested ultra low power (48.31 pJ/cycle @1MHz per core on 0.18um commercial process).
-Ultra-Compact RISC-V 32RVI compatible microcontroller: dual and single core IP solutions (less than 32k gates per core)
-Include SPI, Bootstrap, UART and SRAM memory controllers.
-Full instruction-set implementation (32RVI 32-bit base integer) with custom special GPIO instructions
-IP is capable of replacing 8 and 16-bit microcontroller solutions while being flexible and expandable to 32-bits, maintaining complete compatibility to RISC-V open-source toolchains.
-Configurable clock-gated 32-bit bus manager: Facilitates power management and integration of other IP blocks to the RISC-V core.

RTL design and implementation of several IP blocks for two 100+ million logic cells ASICs

-Delivered entirely new micro-architecture definition and RTL code for new features in Tx/Rx interfaces including congestion control, port sub-division and virtual lane management (while maintaining compatibility to previous generation ASICs)
-Expanded legacy data crossbar to accommodate new speed and data formats with backwards compatibility
-Enhanced data throughput in legacy TX/RX ports with backwards compatibility
-RTL code developed for a new ARM-based general control manager including integration of SRAM, PVT and proprietary blocks.
-RTL interface to AlphaWave 100Gbps SERDES, including new FEC modules.
-Drove the relation with backend provider on DFT, floorplanning, place & route for both ASICs
-Synthesis verification (all blocks) including post Place & Route timing and power closure in coordination with backend provider.

Our expertise

  • ASIC design and verification
    (Intel, TSMC, XFAB, Global Foundries, 350nm down to 3nm)
  • ASIC custom IP Integration and design (SerDes, PCIe, DACs, ADCs, Sigma-Delta Modulators, Biomedical Sensor, Current Drivers, etc)
  • Floorplanning, Place and route, Clock tree synthesis
  • Timing closure, Power analysis
  • Verification (UVM, testbench design, debug support)
  • Standard bus interfaces (AMBA AHB, APB, AXI, Wishbone, etc.)
  • High speed interfaces (DDR3/4, PCIe, GBE)
  • DSP and signal processing applications
  • Low power techniques and multiple power domain control under the UPF standard
  • Protocol acceleration and Communications
  • Space applications
  • DFT Integration (Scan Chains, JTAG, ATPG, etc)
  • ASIC Design consultation (Architecture Design, Transaction level modeling, systemC)
  • LVS, Physical verification and GDSII generation

CORE DESIGN methodology

AmD Xilinx Logo white and black
Microchip Logo
Siemens logo Black and white
Logo Universal Verification Methodology
Intel FPGA
Logo Intel Quartus and synopsys

FIELDS of interest

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Satellite Communication

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Satellite Platform

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High Performance Computing

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Industrial Instrumentation & Control


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Cloud Systems

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Video Streaming

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Sensor Adquisition & Procesing

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Test Systems