UVM phases are virtual methods defined within the `uvm_component` class. This class can be extended to create custom components such as scoreboards, monitors, and drivers. When extending this class, only the necessary phases are implemented, it is not mandatory to implement all of them.
The primary purpose of UVM phases is to provide a mechanism for synchronization. All components in the testbench execute the same phase in parallel, and they cannot advance to the next phase until all other components have completed the current phase. However, the phases are executed sequentially. For example, the build phase must end in all components before executing the connect phase.
UVM phases can be categorized into three main groups:
Depending on the reference material, the `start_of_simulation` phase may be considered part of either the build phase or the runtime phase. The other build phases, as they do not consume time, are implemented as functions. This is also true for the clean-up phases. The first group of phases is involved in generating and connecting the entire environment, while the last group is used to conclude the simulation, generating reports, performing statistical calculations, closing open files, and so forth.
All phases in the runtime phase, as they consume time, are implemented as tasks. Additionally, each of these phases has a pre-x phase and a post-x phase.
By adding the “+UVM_ADD_TRACE” argument to the test, you can observe the execution order of the phases in your test. The following is an example capture:
The UVM phases are inherent to every UVM test. It is up to the verification engineer's discretion how to implement them, ensuring optimal test results and efficient use of computing resources.
Written by Roberto Millon Tello, Patricio Gallo & Marcelo Pouso
Edited by Adrian Evaraldo
For further inquiries, contact us: info@emtech.com.ar