Integrating Wireshark with UVM enables real-time packet capture and analysis during network simulations. By streaming generated packets directly from UVM to Wireshark using a Python-driven pipe, users gain immediate visibility into network traffic, enhancing debugging efficiency and flexibility.
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In modern high-speed digital systems, precise timing is critical, because signals arriving at the FPGA often exhibit jitter, a small, unintended variation in signal timing. This phenomenon can disrupt the reliability of data sampling, leading to errors in the data acquisition.Our implementation is based on the FMC-01, a FMC board connected to a Zynq UltraScale+ FPGA, developed by Emtech that enables both signal capture and generation with an 8-channel/16-bit ADC (ISLA216P25) working at 200 MSPS and a dual-channel 16-bit DAC processing at 400 MSPS.
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DPI (Direct Programming Interface) in SystemVerilog enables seamless integration with C, Python, MATLAB, and more, enhancing UVM testbenches for advanced verification. Learn how import and export mechanisms work, enabling bidirectional communication with external applications. Discover how to integrate complex algorithms, external libraries, and simulation tools for a more flexible and powerful verification environment.
Interfaces define how systems interact, whether in hardware or software. In this blog, we explore interfaces, backward compatibility, and their impact on long-term system stability. From the Ship of Theseus to FM broadcasting, we examine real-world examples that highlight the importance of designing robust and future-proof systems.
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Synchronize the arrival of data to a DAC from a Zynq Ultrascale+ MPSoC FPGA. The FPGA transmits data samples to a Texas Instruments DAC3283 via an LVDS interface in DDR mode, utilizing LVDS pairs for high-speed communication. LVDS is a widely used signaling standard, valued for its low power consumption, high noise immunity, and suitability for high-performance applications. This synchronization challenge is particularly interesting due to the stringent timing requirements imposed by the DDR mode and the precision required to close timing on the DAC interface at high frequencies. This article explores two options for synchronizing the interface: applying delays to data signals and adjusting the phase between data and clock.
In modern verification environments, UVM sequences serve as the backbone of stimulus generation. This comprehensive guide is divided into two parts, taking you from fundamental concepts to advanced implementation techniques. This is part two.
In modern verification environments, UVM sequences serve as the backbone of stimulus generation. This comprehensive guide is divided into two parts, taking you from fundamental concepts to advanced implementation techniques.
There are three approaches related to functional verification: black-box, white-box, and gray-box. In this work, a gray-box method is proposed to know the value of internal signals to the DUT. A new class called logic analyzer is created and connected to the DUT using the same approach as the agents. The link between the RTL design and verification components is the top module, where the DUT interface (I/O ports) connects to the virtual interfaces of the agents and, in this case, the logic analyzer.
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In the rapidly changing IoT/AgTech field, Emtech strives to deliver innovative solutions for agriculture. We upgraded from LoRa to LoRaWAN gateways to enable bidirectional communication with our nodes. This led us to adopt Zephyr OS, offering a more robust development experience for LoRaWAN.
In this article, we will explore how to apply the SOLID principles within the context of SystemVerilog for verification purposes. Originally introduced by Robert C. Martin in the early 2000s, the SOLID principles are a set of five guidelines aimed at improving the design and maintainability of object-oriented software. The acronym SOLID was subsequently coined by Michael Feathers to represent these key principles. The five principles are:S - Single Responsibility Principle. O - Open/Closed Principle. L - Liskov Substitution Principle. I - Interface Segregation Principle. D - Dependency Inversion Principle
Last week, our dev team was knee-deep in a project integrating Xilinx's AXI Quad SPI IP into a Petalinux system. Everything seemed to be in order, but they kept hitting a wall when trying to configure the SPI device. After hours of troubleshooting, and a few dips into linux kernel driver debug features (more on this on future posts!), they finally stumbled upon a simple solution that saved the day!
Interactive dashboards are an essential tool for visualizing and exploring data. With Python libraries like Pandas and Dash, creating these dashboards becomes straightforward and efficient. During this post, we'll walk you through the process of building a dashboard step by step, from loading and preprocessing the data to creating interactive plots and generating a web-based interface.
The Zephyr Project emerged on the embedded systems scene in 2016 as a new real-time operating system (RTOS) for embedded and IoT devices. It's a collaborative effort led by the Linux Foundation, along with Wind River, Synopsys, and NXP. Their goal was to create a multi-platform RTOS that leverages proven concepts from the Linux operating system, such as kconfig, device trees, and the driver model.
Discover how to effectively use the unique constraint and explore various methods for randomizing sequences in our comprehensive article.
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Developing software based on preexisting code is an art in itself. When this challenge is combined with the use of the Qt framework and an inefficient legacy architecture, the complexity and opportunities multiply. In this blog, we will explore not only the benefits and challenges of inheriting code in the world of Qt but also how to address an inefficient legacy architecture and face the eternal dilemma of investing time in redesign versus saving time by maintaining the existing architecture.
Unlocking the Raspberry Pi's full potential for developing HMI applications for IoT involves a symphony of components, from the nimble Buildroot OS to the versatile OPC UA Server, TCP/IP Server, Serial Interface, RDP, SFTP, Camera, and seamless OS updates. Each element plays a pivotal role in enabling efficient communication, remote access, and adaptability, making it an ideal solution for the challenges of demanding industrial scenarios.
The principles of synchronous digital design state that we must have a clock, which will nicely mark the rhythm of the different signals traversing our device. We can think of this clock as a sort of orchestra director, which will make sure that everyone does its job exactly when it is required - not before, nor after.However, complex digital designs will often have more than one clock domain. When this happens, it is like having a whole new orchestra, playing side by side to the old one. If we keep them away from each other, they will both play independently, each at its own pace - but what happens when we need to make them play together? Which director will the different instruments follow? What happens when one orchestra needs to “borrow” a player from the other one in the middle of the concert? This is the problem we face when dealing with clock domain crossings, or CDCs.
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In an increasingly interconnected world, where electronics span from mobile devices to autonomous vehicles, communication systems and high-precision medical systems, PCB design stands as a crucial foundation for innovation. It provides the physical and electrical structure that enables devices to function correctly and communicate efficiently with each other.
Developing a test where simulation parameters are randomized enables achieving better coverage of the DUT’s state space by simulating different test seeds. This methodology reduces the time required for test creation and maintenance. If a directed test is required, it can be created by adding constraints to the random test.
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In the previous article, we looked at how hardware starts, found the bootloader, loaded the kernel, searched and configured the drivers and started the user space .In this article we must deepen in the user space initialization process.
Today, more than an article, we are giving you a presentation that was made internally to give a small overview of some tools, frameworks and strategies that can help us lead projects or better understand the processes that must be done to successfully meet the projects with the objectives. that we work every day. It is important to gain a deeper understanding of project planning and execution, which is accompanied by challenges and setbacks. When leading complex projects, different types of complexities can arise, from their structure and scope to their changing nature, along with power and political dynamics within the project team and external stakeholders. I hope you like it and can learn a little more about project management.
In today's post we will introduce you to automating industrial or Internet of Things equipment through an API developed with the OPC UA standard using QT as a development platform. QT allows you to create cross-platform applications, so you could create an application that runs both on a PC and on an embedded system like a raspberry pi.
In the previous article, we saw what Linux is, what it is suitable for, and what is the basic structure from a kernel view. In the present article we discussed, deeper, what is the structure of that called userland.
Linux is a very popular operating system in many computer systems and it's a first choice on data centers and high end software infrastructure, but the flexibility of the penguin’s kernel made this to be very suitable for extremely low end devices. Come with me and discover the blessings and curses of the linux kernel in embedded systems, low resource devices and (not-so-)hard-real-time things.
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